Semiconductor device and method of manufacturing a semiconductor device

ABSTRACT

The invention provides a method of producing a semiconductor device conforming to plural supply voltage specifications without increasing the chip size and the production cost, while the device achieves a high-speed performance. The method includes plural processes for forming plural types of MOS transistors supplied with different power supply voltages in correspondence with external power supply voltages, which are comprised of a first process common to the plural types of MOS transistors, a second process following the first process, which is different by each of the plural types of MOS transistors, and a third process following the second process, which is common to the plural types of MOS transistors.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a semiconductor device and amethod of manufacturing the same, specifically to an effective techniquefor use in the semiconductor device incorporating high-speed ICsconforming to plural external supply voltages.

[0002] In general, the supply voltage externally supplied to LSIs formedon a semiconductor chip is not necessarily specified as one type,although the functions of the LSIs are identical. For example, the lowersupply voltage is advantageous for higher-speed, or lower powerconsumption, but the time that the power supply voltage of the systemusing the LSIs is switched into the lower voltage in the market is notclearly foreseen, and the time comes differently depending on the usersor the purposes for use. Some systems require modifying the supplyvoltage specification of the I/O (Input/Output) circuit in view of thenoises against the signal.

[0003] Accordingly, an LSI manufacturer has to develop different LSIswith one and the same function at the same time, in correspondence withthe different specifications of plural external supply voltages. In sucha case, to develop the LSIs with the same function individually by eachof the supply voltage specifications will require enormous design works,which invites an elongated development term and increased productioncost. Therefore, the usual practice searches for common grounds as muchas possible in the specifications of the circuits that can be designedcommonly, thus enhancing the design efficiency.

SUMMARY OF THE INVENTION

[0004] The inventors have examined the circuit configuration of the LSIthat has the same function and conforms to the two types of the externalsupply voltage specifications. The system that the inventors haveexamined will be outlined as follows.

[0005]FIG. 29 illustrates one example of the supply voltagespecifications required for an LSI. The two types of external supplyvoltages (VDD) to be supplied to the LSI are assumed to be 3.3 Vand 2.5V; and the I/O supply voltages (VDDQ) are assumed to be 3.3 V and 2.5 V.The I/O supply voltages (VDDQ) represent the maximum values of the inputsignal levels that are inputted to the LSI. The internal supply voltages(VDDI) (supply voltages for the internal circuits) are assumed to be 1.5V in both specifications.

[0006]FIG. 30 illustrates one example of the gate insulating filmthickness (TOX) and the minimum processing gate length (Lg) of the MOStransistor that is optimized so as to conform to the above three kindsof supply voltages (3.3 V, 2.5 V, 1.5 V). As the supply voltage appliedto the MOS transistor increases, the gate insulating film thickness(TOX) becomes thicker, and the minimum processing gate length (Lg)becomes longer accordingly.

[0007]FIG. 31 illustrates one example of the LSI circuit constructionconforming to the supply voltage specifications shown in FIG. 29. TheLSI (000) is composed of an input circuit (001), step-down circuit(002), internal circuit (101), and output circuit (003). The step-downcircuit (002) lowers the external supply voltage (VDD) to the internalsupply voltage (VDDI), which is supplied to the internal circuit (101).The input circuit (001) and the output circuit (003) are directlysupplied with the input signal (IN) and the I/O supply voltage (VDDQ)that varies depending upon the external supply voltage specifications.

[0008] In the foregoing circuit construction, by designing the step-downcircuit (002) to bring the internal supply voltage (VDDI) into 1.5 V ineither case of the external supply voltage (VDD) being 3.3 V and 2.5 V,the design and manufacturing process of the internal circuit (101) canbe unified into two types of LSIs. That is, in either of the LSIs, theinternal circuit (101) is supplied only with the supply voltage of 1.5V, and the internal circuit can be formed with MOS transistors havingthe withstand voltage of 1.5 V shown in FIG. 30.

[0009] On the other hand, the input circuit (001) and the output circuit(003) are formed with MOS transistors having such a withstand voltagethat prevents breakdown of the gate insulating film even in case of theI/O supply voltage (VDDQ) being high (3.3 V), and the same circuit isalso used in case of the I/O supply voltage (VDDQ) being low (2.5 V).That is, the input circuit (001) and the output circuit (003) areconfigured with the 3.3 V withstanding MOS transistor having the gateinsulating film thickness (TOX)=8 nm and the minimum processing gatelength (Lg)=0.4 μm, as shown in FIG. 30, in either case of the LSI of3.3 V specification and the LSI of 2.5 v specification.

[0010]FIG. 32 is a circuit diagram illustrating the above circuitconstruction in detail, and FIG. 33 illustrates the waveforms of theinternal operations in this circuit. The MOS transistors (f01, f02)constituting the input circuit (001) and the MOS transistors (f03 tof10) constituting the output circuit (003) are supplied with the I/Osupply voltage (VDDQ) and the input signal (IN) that differ depending onthe external supply voltage specifications; therefore, the 3.3 Vwithstanding MOS transistor is used for these, as mentioned above.

[0011] However, if this circuit construction is adopted, the I/O supplyvoltage (VDDQ) is brought into 2.5 V, in case of the LSI with thespecification of the external supply voltage (VDD) being 2.5 V;accordingly, the MOS transistor (005) is supplied with less than 2.5 Vacross the gate and the source thereof. Accordingly, the current drivecapability of the MOS transistors (f01 to f10) is extremely lowered,since these transistors are optimized at 3.3 V, which creates a problemthat increases the delay times of the input circuit (001) and the outputcircuit (003).

[0012]FIG. 34 illustrates the second example of the LSI circuitconstruction conforming to the supply voltage specifications shown inFIG. 29. This example forms inside the LSI (000) the input circuit (001a) and the output circuit (003 a) configured with the 3.3 V MOStransistor having the gate insulating film thickness (TOX)=8 nm and theminimum processing gate length (Lg)=0.4 μm, and the input circuit (001b) and the output circuit (003 b) configured with the 2.5 V MOStransistor. (006) having the gate insulating film thickness (TOX)=6 nmand the minimum processing gate length (Lg)=0.3 μm. Further, when theLSI of 3.3 V specification is manufactured, the wiring (010) of 3.3 Vspecification is connected in the wiring formation step, and when theLSI of 2.5 V specification is manufactured, the wiring (011) of 2.5 Vspecification is formed.

[0013] When the second circuit construction is adopted, it is possibleto avoid the problem of increasing the delay times of the input circuit(001) and the output circuit (003), in the LSI with the specification ofthe external supply voltage (VDD) being 2.5 V. However, in either of theLSI of 2.5 V specification and the LSI of 3.3 V specification, the sizeof the input/output circuit becomes double, compared with the firstcircuit construction, which leads to a problem that increases the chipsize and the production cost.

[0014] The present invention has been made in view of thesecircumstances, and it is an object of the invention to provide a systemthat realizes the high-speed operation of a semiconductor device thatconforms to plural supply voltage specifications.

[0015] Another object of the invention is to provide a system thatreduces the production cost of a semiconductor device conforming toplural supply voltage specifications.

[0016] Another object of the invention is to provide a system thatshortens the development term of a semiconductor device conforming toplural supply voltage specifications.

[0017] The above and other objects and novel features of the inventionwill become apparent from the descriptions and accompanying drawings ofthis specification.

[0018] In accordance with one aspect of the invention, the semiconductordevice includes an input circuit or an output circuit configured with aplurality of first MOS transistors in a first area of a principal planeon a semiconductor substrate, and an internal circuit configured with aplurality of second MOS transistors in a second area of the principalplane on the semiconductor substrate, in which a spacing between a firstgate electrode of the first MOS transistors constituting the inputcircuit or the output circuit and a first contact hole for connecting awiring to a source region or a drain region of the first MOS transistorsis larger than a minimum processing dimension of the spacing between thefirst gate electrode and the first contact hole, and a spacing between asecond gate electrode of the second MOS transistors constituting theinternal circuit and a second contact hole for connecting a wiring to asource region or a drain region of the second MOS transistors is equalto a minimum processing dimension of the spacing between the second gateelectrode and the second contact hole.

[0019] In accordance with another aspect of the invention, thesemiconductor device includes an input circuit or an output circuitconfigured with a plurality of first MOS transistors in a first area ofa principal plane on a semiconductor substrate, and an internal circuitconfigured with a plurality of second MOS transistors in a second areaof the principal plane on the semiconductor substrate, in which aspacing between an edge of a first active region where the first MOStransistors constituting the input circuit or the output circuit areformed and a first contact hole for connecting a wiring to a sourceregion or a drain region of the first MOS transistors is larger than aminimum processing dimension of the spacing between the edge of thefirst active region and the first contact hole, and a spacing between anedge of a second active region where the second MOS transistorsconstituting the internal circuit are formed and a second contact holefor connecting a wiring to a source region or a drain region of thesecond MOS transistors is equal to a minimum processing dimension of thespacing between the edge of the second active region and the secondcontact hole.

[0020] In accordance with another aspect of the invention, the method ofmanufacturing a semiconductor device includes plural processes forforming plural types of MOS transistors to which different power supplyvoltages are applied in correspondence with external power supplyvoltages, in which the plural processes are composed of a process commonto the plural types of MOS transistors and a process different by eachof the plural types of MOS transistors.

[0021] In accordance with another aspect of the invention, the method ofmanufacturing a semiconductor device includes the steps of: forming afirst semiconductor device configured with a plurality of first MOStransistors, which includes an input circuit or an output circuitsupplied with a first external supply voltage, on a principal plane of afirst semiconductor wafer, and forming on the principal plane of asecond semiconductor wafer a second semiconductor device configured witha plurality of second MOS transistors, including an input circuit or anoutput circuit supplied with a second external supply voltage differentfrom the first external supply voltage, which has the same function asthe first semiconductor device. The plural processes that form the firstMOS transistors on the principal plane of the first semiconductor wafer,and the plural processes that form the second MOS transistors on theprincipal plane of the second semiconductor wafer are composed of afirst process common to the first and second MOS transistors, a secondprocess following the first process, which is different in the first MOStransistors and the second MOS transistors, and a third processfollowing the second process, which is common to the first and secondMOS transistors.

BRIEF DESCRIPTION OF THE DRAWINGS

[0022]FIG. 1 is a block diagram of a semiconductor chip thatincorporates an SRAM as one embodiment of the invention;

[0023]FIG. 2 is a block diagram of a semiconductor chip thatincorporates an SRAM as one embodiment of the invention;

[0024]FIG. 3 is a circuit diagram illustrating a data output circuit ofthe SRAM as one embodiment of the invention;

[0025]FIG. 4 is a chart illustrating waveforms of internal operations inthe data output circuit shown in FIG. 3;

[0026]FIG. 5 is a circuit diagram illustrating an address input circuitand a data input register of the SRAM as one embodiment of theinvention;

[0027]FIG. 6 is a chart illustrating the amplitude of the address inputsignal inputted to the address input circuit shown in FIG. 5;

[0028]FIG. 7(a) is a plan view of a 3.3 V withstanding MOS transistorformed on the first silicon chip, and FIG. 7(b) is a plan view of a 1.5V withstanding MOS transistor formed on the second silicon chip;

[0029]FIG. 8(a) is a plan view of a 2.5 V withstanding MOS transistorformed on the first silicon chip, and FIG. 8(b) is a plan view of a 1.5V withstanding MOS transistor formed on the second silicon chip;

[0030]FIG. 9 is a sectional view illustrating a process of manufacturingthe SRAM as one embodiment of the invention;

[0031]FIG. 10 is a sectional view illustrating a process ofmanufacturing the SRAM as one embodiment of the invention;

[0032]FIG. 11 is a sectional view illustrating a process ofmanufacturing the SRAM as one embodiment of the invention;

[0033]FIG. 12 is a sectional view illustrating a process ofmanufacturing the SRAM as one embodiment of the invention;

[0034]FIG. 13 is a sectional view illustrating a process ofmanufacturing the SRAM as one embodiment of the invention;

[0035]FIG. 14 is a sectional view illustrating a process ofmanufacturing the SRAM as one embodiment of the invention;

[0036]FIG. 15 is a sectional view illustrating a process ofmanufacturing the SRAM as one embodiment of the invention;

[0037]FIG. 16 is a sectional view illustrating a process ofmanufacturing the SRAM as one embodiment of the invention;

[0038]FIG. 17 is a sectional view illustrating a process ofmanufacturing the SRAM as one embodiment of the invention;

[0039]FIG. 18 is a sectional view illustrating a process ofmanufacturing the SRAM as one embodiment of the invention;

[0040]FIG. 19 is a plan view and a sectional view illustrating theprocess of manufacturing the SRAM as one embodiment of the invention;

[0041]FIG. 20 is a plan view and a sectional view illustrating theprocess of manufacturing the SRAM as one embodiment of the invention;

[0042]FIG. 21 is a sectional view illustrating a process ofmanufacturing the SRAM as one embodiment of the invention;

[0043]FIG. 22 is a sectional view illustrating a process ofmanufacturing the SRAM as one embodiment of the invention;

[0044]FIG. 23 is a flow chart illustrating a process of manufacturingthe SRAM as one embodiment of the invention;

[0045]FIG. 24 is a flow chart illustrating a process of manufacturingthe SRAM as another embodiment of the invention;

[0046]FIG. 25 is a flow chart illustrating a process of manufacturingthe SRAM as another embodiment of the invention;

[0047]FIG. 26 is a plan view illustrating a MOS transistor of the SRAMas another embodiment of the invention;

[0048]FIG. 27 is a chart illustrating the supply voltage specificationsof the SRAM of the invention;

[0049]FIG. 28 is a plan view illustrating a MOS transistor of the SRAMas another embodiment of the invention;

[0050]FIG. 29 is a chart illustrating one example of the supply voltagespecifications required for an LSI;

[0051]FIG. 30 is a chart illustrating one example of the gate insulatingfilm thickness (TOX) and the minimum processing gate length (Lg) of aMOS transistor to be optimized to conform to the supply voltages shownin FIG. 29;

[0052]FIG. 31 is a block diagram illustrating one example of an LSIcircuit configuration that conforms to the supply voltage specificationsshown in FIG. 29;

[0053]FIG. 32 is a detailed circuit diagram of a part of the circuitshown in FIG. 31;

[0054]FIG. 33 is a chart illustrating the waveforms of internaloperations in the circuit shown in FIG. 32; and

[0055]FIG. 34 is a block diagram illustrating another example of the LSIcircuit configuration that conforms to the supply voltage specificationsshown in FIG. 29.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0056] The preferred embodiments of the invention will be described withreference to the accompanying drawings. The components and membershaving the same functions throughout the drawings are given the samenumeric symbols to avoid the repeated explanations.

[0057] [Embodiment 1]

[0058]FIG. 1 is a circuit block diagram of a silicon chip 1 a where anSRAM (Static Random Access Memory) as one embodiment of the invention isformed. This SRAM is a high-speed SRAM having an 8 Megabit storagecapacity that is used for a cache memory of a workstation or the like.The SRAM includes an internal circuit 101 that is composed of a memorycell array 106 having plural memory cells formed therein, a row decoder107, a column decoder 108, a sense amp/write amp 109, an addressregister 110, a data output register 111, and a data input register 112,etc., and an input/output circuit that is composed of an address inputcircuit 102, a data input circuit 103, a data output circuit 104, and aclock buffer 105. Through a data input/output pad DQ, a data signal isinputted to the data input circuit 103, and is outputted from the dataoutput circuit 104. An address input signal is inputted to the addressinput circuit 102 through an address input pad AD. A clock signal isinputted to the clock buffer 105 through a clock input pad CK.

[0059] The SRAM formed on the silicon chip 1 a is supplied with thelower voltage (2.5 V) of the two types (3.3 V and 2.5 V) of the externalsupply voltages (VDD) as shown in FIG. 29, in correspondence with thespecifications. The I/O supply voltage (VDDQ) being the maximum value ofthe input signal level inputted to the SRAM is 2.5 V, which is the sameas the external supply voltage (VDD). Further, the internal circuit 101is designed to operate with the internal supply voltage (VDDI) of 1.5 V,which is lower than the external supply voltage (VDD), in order forhigher speed and lower power consumption.

[0060]FIG. 2 is a circuit block diagram of an 8 Megabit high-speed SRAMformed on another silicon chip 1 b. This SRAM has the same function asthe SRAM formed on the silicon chip 1 a, and the same degree ofintegration. However, this SRAM is supplied with the higher voltage (3.3V) of the two types (3.3 V and 2.5 V) of the external supply voltages(VDD), in correspondence with the specifications. The I/O supply voltage(VDDQ) being the maximum value of the input signal level inputted tothis SRAM is 3.3 V, which is the same as the external supply voltage(VDD). Further, the internal circuit 101 is designed to operate with theinternal supply voltage (VDDI) of 1.5 V, which is lower than theexternal supply voltage (VDD), in order for higher speed and lower powerconsumption.

[0061] With regard to the SRAM formed on the first silicon chip 1 a andthe SRAM formed on the second silicon chip 1 b, only part of the MOStransistors constituting the input/output circuit are different, but theother circuits are made up with the same MOS transistors. That is, theSRAM formed on the silicon chip 1 a is optimized so that the MOStransistors constituting the input/output circuit can operate at a highspeed with the supply voltage of 2.5 V; and the SRAM formed on thesilicon chip 1 b is optimized so that the MOS transistors constitutingthe input/output circuit can operate at a high speed with the supplyvoltage of 3.3 V. These two types of SRAMs are furnished with thestep-down circuits that supply the internal circuit 101 with theinternal supply voltage (VDDI) of 1.5 V, in either case of 3.3 V and 2.5V for the external supply voltage (VDD).

[0062]FIG. 3 is a concrete circuit diagram of the data output circuit104, and FIG. 4 is a waveform chart illustrating the internal operationsof the data output circuit 104.

[0063] Among the MOS transistors that constitute the data output circuit104, the n-channel MOS transistors (f32, f34, f36) and the p-channel MOStransistors (f31, f33, f35, f37) are directly supplied with the I/Osupply voltage (VDDQ) that differs depending on the external supplyvoltage specifications. Therefore, the MOS transistors (f31 to f37)formed on the silicon chip 1 a are designed to withstand 2.5 V so as toexhibit the high-speed performance when the I/O supply voltage (VDDQ) of2.5 V is supplied thereto. On the other hand, the MOS transistors (f31to f37) formed on the silicon chip 1 b are designed to withstand 3.3 Vso as to exhibit the high-speed performance when the I/O supply voltage(VDDQ) of 3.3 V is supplied thereto. The other MOS transistors of thedata output circuit 104 are designed to withstand 3.3 V for both thesilicon chip 1 a and 1 b, so that they can be used with the two kinds ofsupply voltages (2.5 V, 3.3 V).

[0064]FIG. 5 is a concrete circuit diagram of the address input circuit102 and the data input register 112, and FIG. 6 is a waveform chartillustrating the address input signal AD inputted to the address inputcircuit 102.

[0065] As shown in FIG. 6, usually the address input signal AD is asmall amplitude signal appeared against the reference voltage (VREF);however, when it takes the maximum amplitude, the address input signalAD becomes the same voltage as the I/O supply voltage (VDDQ). Therefore,the MOS transistors (f21 and f22) formed on the silicon chip 1 a aredesigned to withstand 2.5 V so as to exhibit the high-speed performancewhen the I/O supply voltage (VDDQ) of 2.5 V is supplied thereto. On theother hand, the MOS transistors (f21 and f22) formed on the silicon chip1 b are designed to withstand 3.3 V so as to exhibit the high-speedperformance when the I/O supply voltage (VDDQ) of 3.3 V is suppliedthereto.

[0066]FIG. 7(a) is a plan view of the 3.3 V withstanding MOS transistorformed on the silicon chip 1 b, and FIG. 7(b) is a plan view of the 1.5V withstanding MOS transistor formed on the same silicon chip 1 b. The3.3 V withstanding MOS transistor and the 1.5 V withstanding MOStransistor each have the gate insulating film thickness (TOX) and theminimum processing gate length (Lg) as shown in FIG. 30. In the 3.3 Vwithstanding MOS transistor, the spacing between the gate electrode 8 band the contact hole 17 for connecting the source and drain regions tothe wiring region is formed in the minimum processing dimension (a) ofthis spacing, in order to promote the microstructure. Also, in the 1.5 Vwithstanding MOS transistor, the spacing between the gate electrode 8 cand the contact hole 16 for connecting the source and drain regions tothe wiring region is formed in the minimum processing dimension (a) ofthis spacing, for the same reason.

[0067]FIG. 8(a) is a plan view of the 2.5 V withstanding MOS transistorformed on the silicon chip 1 a, and FIG. 8(b) is a plan view of the 1.5V withstanding MOS transistor formed on the same silicon chip 1 a. The2.5 V withstanding MOS transistor and the 1.5 V withstanding MOStransistor each have the gate insulating film thickness (TOX) and theminimum processing gate length (Lg) as shown in FIG. 30.

[0068] The 1.5 V withstanding MOS transistors constituting the SRAMinternal circuit 101 take on the common structure to the silicon chips 1a and 1 b. That is, the 1.5 V withstanding MOS transistor formed on thesilicon chip 1 a and the 1.5 V withstanding MOS transistor formed on thesilicon chip 1 b are formed on an active region 31 that has the samesize, thus having the same gate insulating film thickness (TOX) and thegate length (Lg). Also, the spacing between the gate electrode 8 c andthe contact hole 16 for connecting the source and drain regions to thewiring region is formed identically in the minimum processing dimension(a) of this spacing.

[0069] On the other hand, the 2.5 V withstanding MOS transistor formedon the silicon chip 1 a and the 3.3 V withstanding MOS transistor formedon the silicon chip 1 b are formed on an active region 30 that has thesame size, but the gate insulating film thickness (TOX) and the gatelengths (Lg) of the above two types of transistors are different fromeach other. Therefore, if the spacing between the gate electrode 8 b andthe contact hole 17 of the 3.3 V withstanding MOS transistor is formedin the minimum processing dimension (a) of this spacing, the spacingbetween the gate electrode 8 b and the contact hole 17 of the 2.5 Vwithstanding MOS transistor having the shorter gate length (Lg) will beincreased by α against the minimum processing dimension (a) of thisspacing. Here, α is equal to half the difference between the minimumprocessing gate length (Lg) of the 3.3 V withstanding MOS transistor andthe minimum processing gate length (Lg) of the 2.5 V withstanding MOStransistor.

[0070] Next, the method of manufacturing the SRAM of the 3.3 Vspecification and the SRAM of the 2.5 V specification will be explainedwith reference to FIG. 9 through FIG. 23.

[0071] First, as shown in FIG. 9, a device isolation groove 2 is formedon the principal plane of a silicon wafer 1 (hereunder, also referred toas a substrate) made of the p-type single crystal silicon having aspecific resistance of about 1 to 10 Ωcm. The device isolation groove 2is formed through the processing: etching a device isolation region onthe substrate 1 to form a groove, next depositing a silicon oxide film 3on the substrate 1 including the inside of the groove by means of theCVD method, and then polishing to remove the silicon oxide film 3 on theoutside of the groove by means of the CMP (Chemical MechanicalPolishing).

[0072] Next, as shown in FIG. 10, the processing advances to executingthe ion implantation of the n-type impurities (for example, phosphorus)to one part of the substrate 1, and executing the ion implantation ofthe p-type impurities (for example, boron) to the other one part of thesubstrate 1, and then executing the heat treatment of the substrate 1 todiffuse the impurities, thereby forming the p-type well 4 on the onepart of the substrate 1 and the n-type well 5 on the other one partthereof.

[0073] The manufacturing method in this embodiment stores multiplesheets of the silicon wafers 1 on which the above wells (p-type well 4,n-type well 5) have been formed, by each lot. After the productionquantities of the SRAM of the 3.3 V specification and the SRAM of the2.5 V specification are fixed, these silicon wafers 1 are classifiedinto a silicon wafer 1A used for manufacturing the SRAM of the 2.5 Vspecification and a silicon wafer 1B used for manufacturing the SRAM ofthe 3.3 V specification, and the following processing is applied to thesilicon wafer 1A and the silicon wafer 1B.

[0074] First, as shown in FIG. 11(a), after the surface of the siliconwafer 1A of the 2.5 V specification is cleaned with hydrofluoric acid,the wet oxidation is applied to form a clean silicon oxide film 6 a oneach of the surfaces of the p-type well 4 and the n-type well 5. Also,as shown in FIG. 11(b), after the surface of the silicon wafer 1B of the3.3 V specification is cleaned with hydrofluoric acid, the wet oxidationis applied to form a clean silicon oxide film 6 b on each of thesurfaces of the p-type well 4 and the n-type well 5. The wet oxidationto the silicon wafer 1B takes a longer time (or applies a highertemperature) in comparison to the silicon wafer 1A, so that thethickness of the silicon oxide film 6 b is made slightly thicker thanthat of the silicon oxide film 6 a.

[0075] Next, as shown in FIG. 12(a), the input/output circuit area ofthe silicon wafer 1A is overlaid with a photo resist film 40, and thewet etching with hydrofluoric acid is applied thereon, to remove thegate insulating film 6 a in the internal circuit area. Also, as shown inFIG. 12(b), the input/output circuit area of the silicon wafer 1B isoverlaid with a photo resist film 41, and the same method as above isapplied to remove the gate insulating film 6 b in the internal circuitarea.

[0076] Next, after the photo resist film 40 on the silicon wafer 1A isremoved, as shown in FIG. 13(a), the wet oxidation is applied to thesilicon wafer 1A, whereby a gate oxide film 7 c of 3 nm thick is formedon each of the surfaces of the p-type well 4 and the n-type well 5 inthe internal circuit area. This wet oxidation will thicken the siliconoxide film 6 a in the input/output circuit area, which forms a gateoxide film 7 a of 6 nm thick on each of the surfaces of the p-type well4 and the n-type well 5 in the input/output circuit area.

[0077] Also, after the photo resist film 41 on the silicon wafer 1B isremoved, as shown in FIG. 13(b), the wet oxidation is applied to thesilicon wafer 1B, whereby the gate oxide film 7 c of 3 nm thick isformed on each of the surfaces of the p-type well 4 and the n-type well5 in the internal circuit area. This wet oxidation will thicken thesilicon oxide film 6 b in the input/output circuit area, which forms agate oxide film 7 b of 8 nm thick on each of the surfaces of the p-typewell 4 and the n-type well 5 in the input/output circuit area.

[0078] Next, as shown in FIG. 14(a), a gate electrode 8 a of the gatelength 0.3 μm is formed in the input/output circuit area of the siliconwafer 1A, and the gate electrode 8 c of the gate length 0.14 μm isformed in the internal circuit area. The gate electrodes 8 a, 8 c areformed in an example through the processing of: depositing an n-typepolycrystal silicon film on the silicon wafer 1A by the CVD method, andthereafter patterning this polycrystal silicon film by the dry etchingwith the photo resist film served as the mask.

[0079] Next, as shown in FIG. 14(b), the gate electrode 8 b of the gatelength 0.4 μm is formed in the input/output circuit area of the siliconwafer 1B, and the gate electrode 8 c of the gate length 0.14 μm isformed in the internal circuit area. The gate electrodes 8 b, 8 c areformed in the same manner as the gate electrodes 8 a, 8 c, by patterningthe n-type polycrystal silicon film deposited on the silicon wafer 1B.

[0080] Next, as shown in FIG. 15(a), the ion implantation is executed tothe p-type well 4 of the silicon wafer 1A with the n-type impurities(phosphorous or arsenic) to thereby form an n⁻-type semiconductor region10, and the ion implantation is executed to the n-type well 5 with thep-type impurities (boron) to thereby form a p⁻-type semiconductor region11. Also, as shown in FIG. 15(b), the ion implantation is executed tothe p-type well 4 of the silicon wafer 1B with the n-type impurities(phosphorous or arsenic) to thereby form the n⁻-type semiconductorregion 10, and the ion implantation is executed to the n-type well 5with the p-type impurities (boron) to thereby form the p⁻-typesemiconductor region 11. Here, the n⁻-type semiconductor region 10 andthe p⁻-type semiconductor region 11 are formed to construct the MOStransistor into the LDD (lightly doped drain) structure.

[0081] Next, as shown in FIG. 16(a), a silicon nitride film is depositedon the silicon wafer 1A by the CVD method, and thereafter an anisotropicdry etching is applied to this silicon nitride film to thereby form aside wall spacer 12 on each of the side walls of the gate electrodes 8b, 8 c. Also, as shown in FIG. 16(b), the silicon nitride film isdeposited on the silicon wafer 1B by the CVD method, and thereafter theanisotropic dry etching is applied to this silicon nitride film tothereby form the side wall spacer 12 on each of the side walls of thegate electrodes 8 b, 8 c.

[0082] Next, as shown in FIG. 17(a), the ion implantation is executed tothe p-type well 4 of the silicon wafer 1A with the n-type impurities(phosphorous or arsenic) to thereby form an n⁺-type semiconductor region(source, drain region) 13, and the ion implantation is executed to then-type well 5 with the p-type impurities (boron) to thereby form ap⁺-type semiconductor region (source, drain region) 14. Also, as shownin FIG. 17(b), the ion implantation is executed to the p-type well 4 ofthe silicon wafer 1B with the n-type impurities (phosphorous or arsenic)to thereby form the n⁺-type semiconductor region (source, drain region)13, and the ion implantation is executed to the n-type well 5 with thep-type impurities (boron) to thereby form the p⁺-type semiconductorregion (source, drain region) 14.

[0083] The process up to here forms 2.5 V withstanding n-channel MOStransistors Fna and p-channel MOS transistors Fpa in the input/outputcircuit area of the silicon wafer 1A, and 1.5 V withstanding n-channelMOS transistors Qn and p-channel MOS transistors Qp in the internalcircuit area. Also, the process forms 3.3 V withstanding n-channel MOStransistors Fnb and p-channel MOS transistors Fpb in the input/outputcircuit area of the silicon wafer 1B, and the 1.5 V withstandingn-channel MOS transistors Qn and p-channel MOS transistors Qp in theinternal circuit area.

[0084] Next, as shown in FIG. 18(a), the process deposits a siliconoxide film 15 on the silicon wafer 1A by the CVD method, thereafterapplies the dry etching to the silicon oxide film 15 with the photoresist film (not illustrated) served as the mask, and thereby formscontact holes 17 above each of the source and drain regions (n⁺-typesemiconductor region 13, p⁺-type semiconductor region 14) of then-channel MOS transistors Fna and p-channel MOS transistors Fpa in theinput/output circuit area, and forms contact holes 16 above each of thesource and drain regions (n⁺-type semiconductor region 13, p⁺-typesemiconductor region 14) of the n-channel MOS transistors Qn andp-channel MOS transistors Qp in the internal circuit area.

[0085] Also, as shown in FIG. 18(b), the process deposits a siliconoxide film 15 on the silicon wafer 1B by the CVD method, thereafterapplies the dry etching to the silicon oxide film 15 with the photoresist film (not illustrated) served as the mask, and thereby formscontact holes 17 above each of the source and drain regions (n⁺-typesemiconductor region 13, p⁺-type semiconductor region 14) of then-channel MOS transistors Fnb and p-channel MOS transistors Fpb in theinput/output circuit area, and forms contact holes 16 above each of thesource and drain regions (n⁺-type semiconductor region 13, p⁺-typesemiconductor region 14) of the n-channel MOS transistors Qn andp-channel MOS transistors Qp in the internal circuit area.

[0086] As shown in FIG. 19, in regard to the 3.3 V withstandingn-channel MOS transistors Fnb and p-channel MOS transistors Fpb that areformed in the input/output circuit area of the silicon wafer 1B, thespacing between the gate electrode 8 b and the contact holes 17 forconnecting the wiring regions to the source and drain regions (n⁺-typesemiconductor region 13, p⁺-type semiconductor region 14) is formed inthe minimum processing dimension (a) of this spacing. Also, in the 1.5 Vwithstanding n-channel MOS transistors Qn and p-channel MOS transistorsQp formed in the internal circuit area, the spacing between the gateelectrode 8 c and the contact holes 16 for connecting the wiring regionsto the source and drain regions (n⁺-type semiconductor region 13,p⁺-type semiconductor region 14) is formed in the minimum processingdimension (a) of this spacing.

[0087] As shown in FIG. 20, the 2.5 V withstanding n-channel MOStransistors Fnb and p-channel MOS transistors Fpb formed in theinput/output circuit area of the silicon wafer 1A are formed on theactive region 30 that has the same size as the active region 30 wherethe 3.3 V withstanding n-channel MOS transistors Fnb and p-channel MOStransistors Fpb are formed. Therefore, with regard to the 2.5 Vwithstanding n-channel MOS transistors Fnb and p-channel MOS transistorsFpb, the spacing between the contact holes 17 and the gate electrode 8 ais increased in comparison to the minimum processing dimension (a) ofthis spacing.

[0088] Next, as shown in FIG. 21, metal wirings 20 to 27 are formed onthe silicon wafer 1A; and, as shown in FIG. 22, metal wirings 20 to 27are formed on the silicon wafer 1B. The metal wirings 20 to 27 areformed, for example, through the processing of: depositing an aluminumalloy film on the silicon oxide film 15 including the insides of thecontact holes 16, 17 by the sputtering method, and patterning thealuminum alloy film by the dry etching with the photo resist film servedas the mask. The metal wirings 20 to 27 on the silicon wafer 1A and themetal wirings 20 to 27 on the silicon wafer 1B are formed in the samemanner with the same photo mask.

[0089] The actual SRAM has the metal wirings of about three layers tooverlie the metal wirings 20 to 27, but the detailed explanation will beomitted. These metal wirings are formed by the same system using thesame photo mask to the silicon wafer 1A and the silicon wafer 1B, as themetal wirings 20 to 27. Thereafter, the silicon wafer 1A is divided intoplural silicon chips 1 a, and the silicon wafer 1B is divided intoplural silicon chips 1 b, thus attaining the silicon chip 1 a in whichthe SRAM of 2.5 V specification is formed, as shown in FIG. 1, and thesilicon chip 1 b in which the SRAM of 3.3 V specification is formed, asshown in FIG. 2.

[0090] Thus, according to this embodiment, in the construction of theSRAM of 2.5 V specification, the input/output circuit is configured withthe 2.5 V withstanding MOS transistors, and in the construction of theSRAM of 3.3 V specification, the input/output circuit is configured withthe 3.3 V withstanding MOS transistors. Thereby, both the 2.5 Vwithstanding MOS transistors and the 3.3 V withstanding MOS transistorsattain the sufficient current drive capability, and the SRAMs of bothspecifications will achieve a higher performance speed of theinput/output circuit.

[0091] Further, according to this embodiment, the input/output circuitconfigured with the 2.5 V withstanding MOS transistors and theinput/output circuit configured with the 3.3 V withstanding MOStransistors are not needed to be formed in one and the same chip, whichrestricts the increase of the chip size, thus leading to an inexpensivehigh-speed SRAM.

[0092] Further, according to this embodiment, the greater part of themanufacturing process can be made common as to the two types of SRAMsconforming to the specifications of the external supply voltages, whichlightens the design work in comparison to the case of designing theSRAMs of the same function individually by each of the supply voltagespecifications, thereby shortening the development term and reducing themanufacturing cost.

[0093] Furthermore, according to this embodiment, the arrangements onproduction can be made which store the silicon wafers having completedpart of the manufacturing process common to the two types of the SRAMs,and after fixing the production quantities, manufacture the two types ofthe SRAMs with the silicon wafers. Thereby, the term form the receipt oforder to the delivery can be shortened.

[0094] [Embodiment 2]

[0095] In the foregoing embodiment 1, the gate insulating film thickness(TOX) and the gate length (Lg) of the 3.3 V withstanding MOS transistorare specified as 8 nm and 0.4 μm, respectively; and the gate insulatingfilm thickness (TOX) and the gate length (Lg) of the 2.5 V withstandingMOS transistor are specified as 6 nm and 0.3 μm, respectively. However,as shown in FIG. 24, the gate insulating film thickness (TOX) of the 3.3V withstanding MOS transistor may be specified as 8 nm, the gateinsulating film thickness (TOX) of the 2.5 V withstanding MOS transistoras 6 nm, and the gate length (Lg) as 0.4 μm, as being common to both.

[0096] Further, as shown in FIG. 25, the additional ion implantation maybe conducted to the channel formed areas for the 3.3 V withstanding MOStransistor, so as to achieve a high-speed operation at the supplyvoltage 3.3 V, for further optimization.

[0097] Further, as shown in FIG. 26, the arrangements maybe made in sucha manner that the spacing (c) between the contact hole 17 of the 3.3 Vwithstanding MOS transistor and the edge of the active region 30 is madeequal to the minimum processing dimension (a) of the spacing between thecontact hole 17 and the gate electrode 8 b, and the spacing (c′) betweenthe contact hole 17 of the 2.5 V withstanding MOS transistor and theedge of the active region 30 is made larger by α than the minimumprocessing dimension (a) of the spacing between the contact hole 17 andthe gate electrode 8 a. Here, α is equal to half the difference betweenthe minimum processing gate length (Lg) of the 3.3 V withstanding MOStransistor and the minimum processing gate length (Lg) of the 2.5 Vwithstanding MOS transistor.

[0098] In case of the 2.5 V withstanding MOS transistor, the spacingbetween the contact hole 17 and the gate electrode 8 a becomes equal tothe minimum processing dimension (a), which restricts the decrease ofcurrents by diffused resistors.

[0099] Further, as shown in FIG. 27, in a case that the lower I/O supplyvoltage (VDDQ) is equal to the internal supply voltage (VDDI), theinput/output circuit of the 2.5 V specification can be configured withthe 1.5 V withstanding MOS transistor, in the same manner as theinternal circuit. In this case, all the MOS transistors in the SRAM of2.5 V specification are made up with one kind of gate insulating film,which permits a further reduction of the manufacturing process.

[0100] The embodiments having been described concretely, it is naturalthat the invention is not limited to the above embodiments, and variousmodifications and changes will be possible without departing from thespirit and scope of the invention.

[0101] The above embodiments have related the SRAM conforming to twotypes of external supply voltage specifications as an example, howeverthe invention can be applied in general to a semiconductor device havinghigh-speed ICs conforming to plural external supply voltagespecifications.

[0102] The invention exhibits the following effects as typical ones.

[0103] The invention achieves a high-speed performance of asemiconductor device conforming to plural supply voltage specifications.

[0104] The invention achieves a reduction of the manufacturing cost of asemiconductor device conforming to plural supply voltage specifications.

[0105] The invention achieves a shortening of the development term of asemiconductor device conforming to plural supply voltage specifications.

What is claimed is:
 1. A semiconductor device including an input circuitor an output circuit configured with a plurality of first MOStransistors in a first area of a principal plane on a semiconductorsubstrate, and an internal circuit configured with a plurality of secondMOS transistors in a second area of the principal plane on thesemiconductor substrate, wherein a spacing between a fist gate electrodeof the first MOS transistors constituting the input circuit or theoutput circuit and a first contact hole for connecting a wiring to asource region or a drain region of the first MOS transistors is largerthan a minimum processing dimension of the spacing between the firstgate electrode and the first contact hole, and wherein a spacing betweena second gate electrode of the second MOS transistors constituting theinternal circuit and a second contact hole for connecting a wiring to asource region or a drain region of the second MOS transistors is equalto a minimum processing dimension of the spacing between the second gateelectrode and the second contact hole.
 2. A semiconductor deviceincluding an input circuit or an output circuit configured with aplurality of first MOS transistors in a first area of a principal planeon a semiconductor substrate, and an internal circuit configured with aplurality of second MOS transistors in a second area of the principalplane on the semiconductor substrate, wherein a spacing between an edgeof a first active region in which the first MOS transistors constitutingthe input circuit or the output circuit are formed and a first contacthole for connecting a wiring to a source region or a drain region of thefirst MOS transistors is larger than a minimum processing dimension ofthe spacing between the edge of the first active region and the firstcontact hole, and wherein a spacing between an edge of a second activeregion in which the second MOS transistors constituting the internalcircuit are formed and a second contact hole for connecting a wiring toa source or a drain region of the second MOS transistors is equal to aminimum processing dimension of the spacing between the edge of thesecond active region and the second contact hole.
 3. A semiconductordevice according to claim 1 or claim 2, wherein a power supply voltageapplied to the first MOS transistors constituting the input circuit orthe output circuit is equal to a power supply voltage applied to thesecond MOS transistors constituting the internal circuit.
 4. Asemiconductor device according to claim 2 or claim 3, wherein a gatelength of the first MOS transistors is equal to a gate length of thesecond MOS transistors.
 5. A semiconductor device according to claim 3,wherein a gate insulating film thickness of the first MOS transistors isequal to a gate insulating film thickness of the second MOS transistors.6. A semiconductor device according to claim 3, wherein an area of theactive region in which the first MOS transistors are formed is largerthan an area of the active region in which the second MOS transistorsare formed.
 7. A semiconductor device according to claim 1 or claim 2,wherein a power supply voltage applied to the first MOS transistorsconstituting the input circuit or the output circuit is higher than apower supply voltage applied to the second MOS transistors constitutingthe internal circuit.
 8. A method of manufacturing a semiconductordevice having plural processes for forming plural types of MOStransistors to which different power supply voltages are applied incorrespondence with external power supply voltages, wherein the pluralprocesses are comprised of a process common to the plural types of MOStransistors and a process different by each of the plural types of MOStransistors.
 9. A method of manufacturing a semiconductor deviceaccording to claim 8, wherein the plural processes are comprised of afirst process common to the plural types of MOS transistors, a secondprocess following the first process, which is different by each of theplural types of MOS transistors, and a third process following thesecond process, which is common to the plural types of MOS transistors.10. A method of manufacturing a semiconductor device according to claim9, wherein the second process includes a process that forms plural typesof gate insulating films of which thickness are different from eachother.
 11. A method of manufacturing a semiconductor device according toclaim 9, wherein the second process includes a process that forms pluraltypes of gate electrodes of which gate lengths are different from eachother.
 12. A method of manufacturing a semiconductor device according toclaim 11, wherein areas of active regions where the plural types of gateelectrodes are formed are equal to each other.
 13. A method ofmanufacturing a semiconductor device according to claim 9, wherein thesecond process includes a process that forms plural types of channelformed areas of which impurity concentrations are different from eachother.
 14. A method of manufacturing a semiconductor device according toclaim 9, wherein the first process includes a process that forms a wellon the semiconductor substrate.
 15. A method of manufacturing asemiconductor device according to claim 8, wherein the plural types ofMOS transistors are MOS transistors that constitute an input circuit oran output circuit.
 16. A method of manufacturing a semiconductor devicecomprising the steps of: forming a first semiconductor device configuredwith a plurality of first MOS transistors, which includes an inputcircuit or an output circuit supplied with a first external supplyvoltage, on a principal plane of a first semiconductor wafer, andforming on the principal plane of a second semiconductor wafer a secondsemiconductor device configured with a plurality of second MOStransistors, including an input circuit or an output circuit suppliedwith a second external supply voltage different from the first externalsupply voltage, which has the same function as the first semiconductordevice, wherein the plural processes that form the first MOS transistorson the principal plane of the first semiconductor wafer, and the pluralprocesses that form the second MOS transistors on the principal plane ofthe second semiconductor wafer are comprised of a first process commonto the first and second MOS transistors, a second process following thefirst process, which is different in the first MOS transistors and thesecond MOS transistors, and a third process following the secondprocess, which is common to the first and second MOS transistors.
 17. Amethod of manufacturing a semiconductor device according to claim 16,wherein the second process includes a process that forms two types ofgate insulating films of which thickness are different from each other.18. A method of manufacturing a semiconductor device according to claim16, wherein the second process includes a process that forms two typesof gate electrodes of which gate lengths are different from each other.19. A method of manufacturing a semiconductor device according to claim16, wherein the second process includes a process that forms two typesof channel formed areas of which impurity concentrations are differentfrom each other.
 20. A method of manufacturing a semiconductor deviceaccording to claim 16, wherein an area of a first active region wherethe first MOS transistors are formed is equal to an area of a secondactive region where the second MOS transistors are formed, wherein aspacing between a fist gate electrode of the first MOS transistors and afirst contact hole for connecting a wiring to a source region or a drainregion of the first MOS transistors is larger than a minimum processingdimension of the spacing between the first gate electrode and the firstcontact hole, and wherein a spacing between a second gate electrode ofthe second MOS transistors and a second contact hole for connecting awiring to a source region or a drain region of the second MOStransistors is equal to a minimum processing dimension of the spacingbetween the second gate electrode and the second contact hole.